Unipolar transistors have an over square increase of resistance Ron with an intended breakthrough voltage according to the estimation:Ron=W/e*μ*ND=8.3*10−9VBR2.5 
wherein
Ron resistance;
W width of spatial charge zone;
e elementary charge;
μ movability
ND doping of drift zone
VBR breakthrough voltage
Thus, vertical DMOS transistors as unipolar transistors for use in power electronics have an excessively high resistance for high breakthrough voltages and thus very high power losses.
This can be improved by additional injection of minority charge carriers, as it is the case for IGBTs that are often providing breakthrough voltages of 600 V and above. However, this is detrimental for switching times since the additionally injected charge carriers first have to be recombined when switching off. The components are thus not suited for fast switching applications based on their high switching losses. Furthermore, the IGBT requires a minimum source drain voltage at the level of the flow voltage of the emitter substrate diode in a range of approximately 0.6 V to 0.8 V so that a substantial drain current can flow.
This means that the IGBT has inferior Ron properties than a comparable vertical DMOS transistor for small source to drain voltages in the range of below 1 V up to approximately 1.5 V.
Dielectrically insulated (switching) high voltage components with unipolar and bipolar conductive mechanisms are known.
In U.S. Pat. No. 5,378,920, a dielectrically insulated high voltage component is illustrated in a thin high resistance semiconductor layer, wherein the high voltage component is insulated from the rest of the semiconductor wafer through oxide layers 102 and 103. The island 104 in which the component is disposed has very small n-doping, cf. FIG. 26 or FIG. 30 of the cited document. An n-layer with low doping is arranged at the base of the island or above the embedded horizontal oxide 102. In a blocking condition, a high breakthrough voltage can be facilitated through a charge carrier depletion of the layers 104, 106 and 109, cf. the FIGS. 25, 26 of the printed document. In case of FIG. 26, a pt doped layer 120 is arranged adjacent to the vertical oxide layer. The component itself is laterally arranged, wherein the drain area is formed from a pt doped portion 119 adjacent to the vertical isolation. The component is a lateral p-channel DMOS-transistor. In the lateral n-channel IGBT illustrated in FIG. 30 of the printed document the drain area 119a or 119b is also adjacent to the vertical isolation or oxide layer 103. The drain area itself is made from a highly doped pt area 119a which is arranged completely within an n-doped portion 119a, 
EP-A 721 211 also illustrates a horizontally arranged transistor for “high” voltages in SOI wafers. The n-channel-IGBT is thus arranged in a low p doped island 4a, wherein a highly doped pt layer 6 is arranged above the horizontally embedded oxide layer 3a and laterally from the vertical oxide layer 3b. The source area includes an n-doped source portion 8 within a p-trough 7. The drain or the emitter of the IGBT is a p-area 11 within an n-area 9, configured as buffer layer. An n-doped area 10 between the gate electrodes 12 and 13 and the n-buffer 9 is used as a drift zone. The illustrated IGBT (therein FIGS. 1 and 3) or the illustrated MOSFET (therein FIG. 4) includes lateral RESURF-transistors in which the n-doped drift zone 10 is cleared from charge carriers based on the vertical and horizontal spatial charge zones.
Extending from the source electrode 14, the source potential lies over the p-trough 7 and the doped layer is arranged adjacent to the isolation trench 6 or the doped layer above the embedded oxide layer 6 in the volume. Thus, a vertical and a horizontal electric field (RESURF-principle) affect the drift zone 10.
The current flow between source and drain is limited by design to the n-doped areas proximal to the surface.
A lateral IGBT in a trench-isolated SOI wafer is also shown in EP-A 649 175. An n+ doped source area 5, which is embedded in a p-trough or in a p-channel area 6, is arranged on the source side. This p-doped area 6 extends from the surface of the silicon at the side of the isolation trench 4 to the embedded oxide 2. An n-doped island 11 is arranged at the drain side, wherein an n+ doped connection area 14 and an emitter structure 12 are arranged within the island.
An externally controllable resistor circuit allows dividing or switching the current flow to the emitter structure or the connection structure. Thus, a quicker switch-off of the transistor shall be facilitated through external switch-off of the emitter structure. However, this requires an additional resistor circuit.
A similar source structure is illustrated in DE-C 198 28 669. The lateral IGBT illustrated therein implemented in trench-isolated SO wafers is made on the source side from an n doped source zone 4 which is embedded in a base zone of the second conductivity type 3. This base area 3 extends from the surface of the silicon at the side of the isolation trench 12 to the doped anode zone 2 within a surrounding n+ island 13. In the drain zone proximal to the embedded insulation layer 10 there are laterally configured portions of the second conductivity type 11. These portions are configured for quicker removal of the stored charge when switching off the IGBT. However, it is disadvantageous that the embedded portions 11 already have to be introduced during the production of the SOI wafer (during wafer production.) It is an additional disadvantage that the portions 11 are subject to all high temperature processes of the subsequent additional wafer process and thus are subject to high levels of diffusion.